The DSP56374 is designed to support a multitude of digital signal processing applications requiring a lot of horsepower in a small package. While the DSP56374 is designed with flexibility and thus is versatile in the types of applications it can support, it does include a powerful set of audio features, including various built-in audio peripherals and embedded software designed to meet the needs of both consumer and automotive audio applications.

The DSP56374 provides a wealth of audio processing functions including an operating system, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, and many more. The DSP56374 also supports various matrix decoders and sound field processing algorithms.

The DSP56374 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale Symphony^TM DSP family. This design provides a two-fold performance increase over Freescale’s popular DSP56000 core family of DSPs while retaining code compatibility.

Significant architectural enhancements include a barrel shifter, 24-bit addressing, patch module, and direct memory access (DMA). The DSP56374 is available in either a 52-pin or 80-pin TQFP at 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1.25 V.

特性

Multimode, multichannel decoder software functionality

Dolby and/or DTS license required

• Dolby Digital
• ProLogic II
• Dolby Headphone (DH)
• Dolby Virtual Speaker (DVS)

Digital Signal Processing Core

• 1.25 V core with a 3.3 V peripheral I/O.
• 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25V (0 deg C to 70 deg C for consumer-grade devices; -40 deg C to 85 deg C for automotive devices)
• Object Code Compatible with the DSP56000 core with highly parallel instruction set 
• Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support
• Program Control with position independent code support and instruction cache support
• Six-channel DMA controller
• Low jitter, PLL based clocking with a wide range of frequency multiplications (1 to 1024), predivider factors (1 to 32) and power saving clock divider (2i: i=0 to 7). Reduces clock noise
• Internal address tracing support and OnCE for Hardware/Software debugging
• JTAG port
• Very low-power CMOS design, fully static design with operating frequencies down to DC
• STOP and WAIT low-power standby modes

On-chip Memory Configuration

• 4K - 6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM.
• 4K - 10Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM.
• 20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism.
• 2K - 10Kx24 Bit Program RAM.
• Various memory switches available

Peripheral modules

• Enhanced Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols.
• Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols. Note 80 pin package only.
• Serial Host Interface (SHI): SPI and I2C protocols, multi master capability in I2C mode, 10-word receive FIFO, support for 8, 16 and 24-bit words.
• Triple Timer module (TEC).
• Hardware Watchdog Timer.
• Most pins of unused peripherals may be programmed as GPIO lines. Up to 47 pins can be configured as GPIO on the 80-pin package and 20 pins on the 52-pin package.