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 型号:DSPB56367AG150
规格书下载
 厂家:Freescale
 年份:15+
 封装:LQFP-144
 数量:
 价格:请联系我们
 备注:
详细介绍:

A new level of affordable audio performance will be within the reach of consumer companies in the audio marketplace thanks to the new SymphonyTM  audio digital signal processor (DSP) chip from Freescale. 

With performance of 150 MIPS the DSP56367 provides the capability to process all the major multi-channel audio decoding standards (Dolby Digital, DTS, MPEG2 Multichannel and AAC, and DVD-audio) along with Dolby Headphone in a single device. It also allows up to 100 MIPs to handle other audio processing requirements such as subwoofer management, soundfield effects, 3D virtual surrounds, equalization, THX+Surround EX, DTS-ES, and Prologic II. The DSP56367 is an enhanced version of Freescales popular DSP56362/6 products. It offers increased performance in a pin-for-pin compatible device with a core that operates at both 1.8V and 1.5V for reduced power consumption. With the same memory map and peripherals as the DSP56366, the DSP56367 allows customers an easy migration path to higher performance at lower power.

特性

Multimode, multichannel decoder software functionality

Dolby and/or DTS license required

  • Dolby Digital
  • DTS
  • DTS - ES
  • DTS Neo6
  • Prologic II
  • DTS 96/24
  • AAC Decoders

Post-processing capabilities

  • Bass management
  • Volume management
  • Delay management
  • Dolby ProLogic
  • Auxiliary mix down
  • Auto detection

Digital Signal Processing Core

  • 150 MIPS with a 150 MHz clock at 1.8 V core with a 3.3 V peripheral I/O OR 100 MIPS with a 100 MHz clock at 1.5 V core with a 3.3 V peripheral I/O
  • Object Code Compatible with the the DSP56000 core with highly parallel instruction set 
  • Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support
  • Program Control with position independent code support and instruction cache support
  • Six-channel DMA controller
  • PLL based clocking with a wide range of frequency multiplications (1 to 4096), predicider factors (1 to 16) and power saving clock divider (2I: i=0 to 7). Reduces clock noise
  • Internal address tracing support and OnCETM for Hardware/Software debugging
  • JTAG port
  • Very low-power CMOS design, fully static design with operating frequencies down to DC
  • STOP and WAIT low-power standby modes

On-chip Memory Configuration

  • 5 K - 7 K x 24 Bit Y-Data RAM and 8 K x 24 Bit Y-Data ROM
  • 8 K - 13 K x 24 Bit X-Data RAM and 32 K x 24 Bit X-Data ROM
  • 40 K x 24 Bit Program ROM
  • 32 K - 10K x 24 Bit Program RAM and 192 x 24 Bit Bootstrap ROM. 1 K of Program RAM may be used as Instruction Cache or for Program ROM patching
  • Various memory switches available

Off-chip memory expansion

  • External Memory Expansion Port
  • Off-chip expansion up to two 16 M x 24-bit word of Data memory
  • Off-chip expansion up to 16 M x 24-bit word of Program memory
  • Simultaneous glueless interface to SRAM and DRAM

Peripheral modules

  • Enhanced Serial Audio Interface (ESAI_0): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols.
  • Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony AC97, network and other programmable protocols. The ESAI_1 shares four of the data pins with ESAI_0, and ESAI_1 does NOT support HCKR and HCKT (high speed clocks)
  • Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16 and 24-bit words.
  • Byte-wide parallel Host Interface (HDI08) with DMA support
  • Triple Timer module
  • Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and AES/EBU digital audio formats
  • Pins of unused peripherals (except SHI) may be programmed as GPIO lines


 


 


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